The present invention relates to a mounting arrangement for an electronic chip carrier.
Chip carriers, such as ceramic chip carriers, are used to enclose sensitive electronic devices that must function in difficult environments such as vacuums. Some applications, such as gun-launched electronics, subject the chip carrier to substantial acceleration forces (g""s) of more than 7000 g""s.
A standard mounting arrangement for mounting a chip carrier 10 to a printed circuit board 12 is shown in FIG. 1. The chip carrier 10, which may be a ceramic chip carrier, is mounted to the printed circuit board 12 by a plurality of J leads 14. The J leads 14 may be copper or a copper alloy and are suitably coupled such as by braising or soldering to the electronics contained within the chip carrier 10. The J leads 14 are also coupled such as by soldering to appropriate elements of the printed circuit board 12.
As can be seen from FIG. 1, the chip carrier 10 is supported above the printed-circuit board 12 by the J leads 14. This mounting arrangement shown in FIG. 1 accommodates mismatches in coefficients of thermal expansion between the chip carrier 10 and the printed circuit board 12. However, the J leads 14 for the chip carrier 10 will not adequately support the chip carrier 10 when subjected to the very high accelerations of some applications such as gun-launch applications.
For example, the chip carrier 10 may weigh as little as one gram. However, at an acceleration of 10,000 times gravity (10,000 g""s), the chip carrier 10 effectively weighs ten kilograms (or twenty-two pounds). That acceleration force can occur in a normal direction, in a shear direction, or in any combination of normal and shear directions relative to the printed circuit board 12. At one gram, the chip carrier 10 may have as many as twenty of the J leads 14 each of which is 0.008 by 0.025 inches in cross-section. At 10,000 g""s, this arrangement results in 5,500 pounds per square inch in shear on the J leads 14, causing the J leads 14 to fail and allow separation between the chip carrier 10 and the printed circuit board 12.
The present invention is directed to an arrangement which overcomes one or more of these or other problems of the prior art.
In accordance with one aspect of the present invention, a mounting arrangement comprises a chip carrier, a mounting structure, and a spacer. The spacer is between the chip carrier and the mounting structure, and the spacer has dimensions so as to transfer g forces from the chip carrier to the mounting structure.
In accordance with another aspect of the present invention, a mounting arrangement comprises a chip carrier, a mounting structure, leads, and a spacer.
The leads couple the chip carrier to the mounting structure so that the chip carrier stands off from the mounting structure. The spacer is between the chip carrier and the mounting structure, and the spacer is reduces g forces on the leads.
In accordance with still another aspect of the present invention, a method of mounting a chip carrier to a mounting structure comprises bonding a spacer to the chip carrier, and bonding the spacer to the mounting structure. The spacer is arranged to transfer g forces from the chip carrier to the mounting structure.
In accordance with a further aspect of the present invention, an assembly comprises a chip carrier, a mounting structure, leads, and a force diverter. The leads are electrically coupled to the chip carrier and to the mounting structure. The force diverter is mechanically coupled to the chip carrier and to the mounting structure, and the force diverter is arranged to divert force generated by the chip carrier from the leads and to the mounting structure.